
/*
**************************************************************************************************************
File:         tb_ddr3.sv
Description:  Defines the testbench required for testing the DDR3 interface
Author     :  Rohit Kulkarni
              Aditya Joshi
**************************************************************************************************************
*/
`include "package.sv"

module tb_ddr3();
  reg CK = 0;
  reg OP, rst; 
  reg [LOGICAL_ADDR_WIDTH-1:0] ADDR;
  reg start;
  wire done;
  
  top TOP(CK,rst,OP,ADDR,start,done);
  
  initial
  begin
    forever #10 CK = ~CK;
end
  
  initial
  begin
    #5 rst = 1;
    #10 rst = 0;
    #10 OP = 1;
    #1 ADDR = 32'habababab;
 	  #1 OP = 1;
 	  #1 start = 1;
    #372
    
    start  = 0; 
    #5 rst    = 1;
    #10 rst   = 0;
    #10 OP = 0;
    #1 ADDR = 32'habababab;
 	  #1 start = 1;
    #30
 	  $stop;
  end
  
  
  
endmodule
